-- -- Dummy VHDL top level file -- library ieee; use ieee.std_logic_1164.all; entity dummy_entity is port ( mclk : in std_logic; reset_n : in std_logic; -- a : in std_logic; b : out std_logic; c : in std_logic_vector(7 downto 0); d : out std_logic_vector(7 downto 0) ); end entity; architecture rtl of dummy_entity is begin end;